{"created":"2023-06-19T09:12:47.841757+00:00","id":24692,"links":{},"metadata":{"_buckets":{"deposit":"84c6178c-949b-481c-82b0-7fc21f6f8dfd"},"_deposit":{"created_by":1,"id":"24692","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"24692"},"status":"published"},"_oai":{"id":"oai:kumadai.repo.nii.ac.jp:00024692","sets":["426:428"]},"author_link":["110470","110467","110468","110466","110469"],"item_16_alternative_title_22":{"attribute_name":"その他の言語のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application : Guide to the Technical Report and Template"}]},"item_16_alternative_title_23":{"attribute_name":"タイトル（ヨミ）","attribute_value_mlt":[{"subitem_alternative_title":"リュウド カヘン ロンリ セル ニ オケル サンジュツ エンザン ムケ ハイセン アーキテクチャ ノ イチ ケントウ"}]},"item_16_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009-01-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicPageEnd":"182","bibliographicPageStart":"177","bibliographicVolumeNumber":"2009","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告. SLDM, [システムLSI設計技術]"}]}]},"item_16_description_17":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_16_description_46":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"論文(Article)","subitem_description_type":"Other"}]},"item_16_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"リコンフィギャラブルIP(Intellectual Property)をSoC(System on a chip)に搭載することで,専用回路であるASIC(Application Specific Integrated Circuit)の性能を生かしつつチップに柔軟性をもたせることができる.しかしながら,代表的なリコンフィギャラブルロジックデバイスのFPGA(Field Programmable Gate Array)をそのままIPとして用いるだけでは性能面で問題がある.そこで我々はリコンフィギャラブルIPとして粒度可変論理セルVGLC(Variable Grain Logic Cell)を提案している.従来のVGLCは汎用的な使用を目的としているのに対し,本稿では算術アプリケーションに特化した配線構造を提案する.データフローグラフより接続構造における特徴量を抽出し,配線構造として用いた場合の評価を行った.結果として,FFT,FIRを対象とした場合,クラスタ内部の論理ブロック数が4の場合に平均して最も実装効率が良くなった.また,両演算を同一の配線構造でマッピングを行う場合,それぞれ個別の配線構造と比較して,配線に要するスイッチ数の増加は33%に抑えられることがわかった.","subitem_description_type":"Other"},{"subitem_description":"A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Intellectual Property (IP) core. However, conventional RLDs,which are commercial Field Programmable Gate Arrays (FPGAs), cannot achieve efficient implementation. Then, we have proposed Variable Grain Logic Cess (VGLC) as a reconfigurable IP core. VGLC is a reconfigurable logic architecture that has both flexibility and high performance. Whereas traditional VGLC assumes general-purpose use, we propose routing architecture specialized in arithmetic applications, in this paper. We extract characteristic in the connection structure from a data flow graph, then think routing architecture using it. As a result, when we target FFT and FIR, four logic block in cluster is improves implementation efficiency most on average. In addition, when both operation are implemented by the same routing architecture, number of swiches increase 33% in comparison with each individual routing architecture.","subitem_description_type":"Other"}]},"item_16_description_77":{"attribute_name":"URL","attribute_value_mlt":[{"subitem_description":"http://ci.nii.ac.jp/naid/110007131448","subitem_description_type":"Other"}]},"item_16_publisher_36":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"一般社団法人情報処理学会"}]},"item_16_relation_16":{"attribute_name":"情報源(ISSN)","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"09196072"}]}]},"item_16_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"一般社団法人情報処理学会"}]},"item_16_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_16_subject_20":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"548","subitem_subject_scheme":"NDC"}]},"item_16_text_18":{"attribute_name":"形態","attribute_value_mlt":[{"subitem_text_value":"758986 bytes"}]},"item_16_text_47":{"attribute_name":"資源タイプ・ローカル","attribute_value_mlt":[{"subitem_text_value":"雑誌掲載論文"}]},"item_16_text_48":{"attribute_name":"資源タイプ・NII","attribute_value_mlt":[{"subitem_text_value":"Journal Article"}]},"item_16_text_49":{"attribute_name":"資源タイプ・DCMI","attribute_value_mlt":[{"subitem_text_value":"text"}]},"item_16_text_50":{"attribute_name":"資源タイプ・ローカル表示コード","attribute_value_mlt":[{"subitem_text_value":"01"}]},"item_16_text_78":{"attribute_name":"コメント","attribute_value_mlt":[{"subitem_text_value":"本文データは学協会の許諾に基づきCiNiiから複製したものである"}]},"item_16_version_type_19":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐藤, 嘉晃"}],"nameIdentifiers":[{"nameIdentifier":"110466","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"趙, 謙"}],"nameIdentifiers":[{"nameIdentifier":"110467","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"尼崎, 太樹"}],"nameIdentifiers":[{"nameIdentifier":"110468","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{"nameIdentifier":"110469","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"末吉, 敏則"}],"nameIdentifiers":[{"nameIdentifier":"110470","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-03-02"}],"displaytype":"detail","filename":"110007131448.pdf","filesize":[{"value":"759.0 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"110007131448.pdf","url":"https://kumadai.repo.nii.ac.jp/record/24692/files/110007131448.pdf"},"version_id":"8c942ce8-e3db-4de1-b1ed-6966728955b6"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"リコンフィギャラブルロジックデバイス","subitem_subject_scheme":"Other"},{"subitem_subject":"配線構造","subitem_subject_scheme":"Other"},{"subitem_subject":"算術演算","subitem_subject_scheme":"Other"},{"subitem_subject":"Data Flow Graph","subitem_subject_scheme":"Other"},{"subitem_subject":"Reconfigurable Logic Device","subitem_subject_scheme":"Other"},{"subitem_subject":"Routing Architecture","subitem_subject_scheme":"Other"},{"subitem_subject":"Arithmetic operation","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"粒度可変論理セルにおける算術演算向け配線アーキテクチャの一検討(バス・配線アーキテクチャ,FPGA応用及び一般)","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"粒度可変論理セルにおける算術演算向け配線アーキテクチャの一検討(バス・配線アーキテクチャ,FPGA応用及び一般)"}]},"item_type_id":"16","owner":"1","path":["428"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-05-11"},"publish_date":"2011-05-11","publish_status":"0","recid":"24692","relation_version_is_last":true,"title":["粒度可変論理セルにおける算術演算向け配線アーキテクチャの一検討(バス・配線アーキテクチャ,FPGA応用及び一般)"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-06-19T18:22:21.533880+00:00"}